Several semiconductor devices have been proposed for use as hot-electron transistors (HET), in which high-energy electrons (hot-electrons) are used. A resonant-tunneling hot-electron transistor (RHET) proposed by Yokoyama, et al., in Document 1 (Japan. J. Appl. Phys. Lett. vol. 24, no. 11, p.L 853, 1985) is the first example of a prior art technique. The resonant-tunneling hot-electron transistor comprises a resonant tunneling structure in an emitter region of the HET. FIG. 9(a) shows the structure of the device disclosed in Document 1, and FIGS. (b)-(d) indicate its operating principle.
Document 1 reports the operation of this device at 77 K. Its operation is as follows. When the base and the emitter shown in FIG. 9(a) are equipotential, the electron energy in the emitter is lower than the quantum level (E1) of the quantum well located between the emitter and the base as shown in FIG. 9(b). For this reason, current does not pass through the emitter. When current is applied across the base and the emitter, the electron energy of the emitter matches the quantum level of the quantum well, as shown in FIG. 9(c), thus generating resonant tunneling. To be more specific, the energy of the electrons in the emitter expands with a certain distribution and only those electrons having the same energy level as the quantum level are emitted to the base layer through the resonant tunneling. Because the emitted electrons have high energy, they quickly pass through the base layer with little scattering, cross over the energy barrier (qΦc) between the base layer, and the collector barrier layer and are implanted into the collector barrier layer. These electrons also travel through the collector barrier layer with little scattering, and eventually reach the collector layer. In the entire process described above, the device can be expected to operate at a higher speed than an ordinary transistor with scattering or diffusion dependency because the momentum of the electrons is almost unaffected by scattering.
The second example of a prior art technique is a device disclosed in Document 2 (Japanese Unexamined Patent Publication No. 1997-326506) by Sugiyama, et al. This device comprises multi-layered fine particles (quantum dots) instead of the resonant tunneling disclosed in Document 1. FIG. 10 shows the structure of the fine-particle layer (a) and the structure of the HET device (b) disclosed in Document 2. As shown in FIG. 10(a), the device of this prior art technique comprises consecutively deposited GaAs interlayers 3a in an HET emitter region 3, and a plurality of fine particles (quantum dots) 3b that are formed in each interlayer 3a by mutual diffusion. This structure aligns quantum dots 3b in each layer in the vertical direction, forming a virtually single quantum dot. Therefore, the device can operate as a carrier filter exhibiting sharp resonant tunneling characteristics and a sharp energy spectrum.
The devices disclosed in the above documents have the following problems. In the device disclosed in Document 1, the operation temperature is limited, the device gain is low, and the operation speed is not as high as could be expected. For example, in Document 1, operation at 77 K is reported; however, neither operation at room temperature nor the operation speed is disclosed. In the same type of RHET devices for which operation at room temperature is disclosed, the gain is lower than that of an ordinary transistor and its operation speed is not very high.
In contrast, the structure of the multi-layered quantum dot in the device disclosed in Document 2 is too complicated to realize. In other words, to achieve the structure shown in FIG. 10(b), fine particles and buried layers are alternately grown on the base layer in a consecutive manner, and it is necessary to control them so that the locations of the fine particles are identical in all of the layers and the shapes of the particles are uniform. If the fine particles in an upper layer are formed in locations different from those in a lower layer during the fabrication process, the structure shown in FIG. 10(b) cannot be achieved. As described above, because an advanced fabrication technique is needed to obtain a three-dimensional arrangement of fine particles in which a great many fine particles are vertically aligned and whose sizes are uniform, it is extremely difficult to achieve this structure.
The present invention aims to solve the problems of the above-described prior art techniques, and provide a semiconductor device that can be easily fabricated and operates at high speed, and a fabrication method thereof.